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applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 1 high performance serial interface circuits S2042/s2043 optical tx optical rx optical rx optical tx s2043 rx S2042 tx s2036 open fiber control (ofc) s2036 open fiber control (ofc) S2042 tx s2043 rx fibre channel controller fibre channel controller bicmos pecl clock generator ? preliminary device specification high performance serial interface circuits S2042/s2043 features ? functionally compliant with ansi x3t11 fibre channel physical and transmission protocol standards ? S2042 transmitter incorporates phase-locked loop (pll) providing clock synthesis from low-speed reference ? s2043 receiver pll configured for clock and data recovery ? 1062, 531 and 266 mb/s operation ? 10- or 20-bit parallel ttl compatible interface ? 1 watt typical power dissipation for chipset ? +3.3/+5v power supply ? low-jitter serial pecl compatible interface ? lock detect ? local loopback ? 10mm x 10mm 52 pqfp package ? fibre channel framing performed by receiver ? continuous downstream clocking from receiver ? ttl compatible outputs possible with +5v i/o power supply applications high-speed data communications ? supercomputer/mainframe ? workstation ? switched networks ? proprietary extended backplanes ? mass storage devices/raid drives general description the S2042 and s2043 transmitter and receiver pair are designed to perform high-speed serial data trans- mission over fiber optic or coaxial cable interfaces conforming to the requirements of the ansi x3t11 fibre channel specification. the chipset is select- able to 1062, 531 or 266 mbit/s data rates with associated 10- or 20-bit data word. the chipset performs parallel-to-serial and serial-to- parallel conversion and framing for block-encoded data. the S2042 on-chip pll synthesizes the high- speed clock from a low-speed reference. the s2043 on-chip pll synchronizes directly to incoming digital signals to receive the data stream. the transmitter and receiver each support differential pecl-compat- ible i/o for fiber optic component interfaces, to minimize crosstalk and maximize data integrity. lo- cal loopback allows for system diagnostics. the ttl i/o section can operate from either a +3.3v or a +5v power supply. with a 3.3v power supply the chipset dissipates only 1w typically. figure 1 shows a typical network configuration incor- porating the chipset. the chipset is compatible with amccs s2036 open fiber control (ofc) device. figure 1. system block diagram
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 2 high performance serial interface circuits S2042/s2043 loopback local loopback is supported by the chipset, and pro- vides a capability for performing offline testing of the interface to ensure the integrity of the serial channel before enabling the transmission medium. it also al- lows for system diagnostics. overview the S2042 transmitter and s2043 receiver provide serialization and deserialization functions for block- encoded data to implement a fibre channel interface. operation of the S2042/s2043 chips is straightfor- ward, as depicted in figure 2. the sequence of operations is as follows: transmitter 1. 10/20-bit parallel input 2. parallel-to-serial conversion 3. serial output receiver 1. clock and data recovery from serial input 2. serial-to-parallel conversion 3. frame detection 4. 10/20-bit parallel output the 10/20-bit parallel data handled by the S2042 and s2043 devices should be from a dc-balanced encod- ing scheme, such as the 8b/10b transmission code, in which information to be transmitted is encoded 8 bits at a time into 10-bit transmission characters. internal clocking and control functions are transparent to the user. details of data timing can be seen in figure 5. a lock detect feature is provided on the receiver, which indicates that the pll is locked (synchronized) to the reference clock or the data stream. S2042 transmitter functional description the S2042 transmitter accepts parallel input data and serializes it for transmission over fiber optic or coaxial cable media. the chip is fully compatible with the ansi x3t11 fibre channel standard, and sup- ports the fibre channel standard's data rates of 1062, 531 and 266 mbit/sec. the parallel input data word can be either 10 bits or 20 bits wide, depending upon dws pin selection. a block diagram showing the basic chip operation is shown in figure 3. figure 3. S2042 functional block diagram control logic test d(0..19) oe1 oe0 dws refclk refsel ratesel 2:1 10 10 20 10 divide-by-2 pll clock multiplier f 0 = f 1 x 10/20 shift register tx ty tlx tly tclk tclkn divide-by-2 dq parallel data in S2042 transmitter s2043 receiver refclk lock detect refclk rclk parallel data out loopback loopback sync serial data tclk figure 2. fibre channel interface diagram
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 3 high performance serial interface circuits S2042/s2043 reference clock input the reference clock input (refclk) must be sup- plied with a single-ended ac coupled crystal clock source with 100 ppm tolerance to assure that the transmitted data meets the fibre channel frequency limits. the internal serial clock is frequency locked to the reference clock. the word rate clock (tclk, tclkn) output frequency is determined by the selected oper- ating speed and word width. refer to table 1 for tclk/tclkn clock frequencies. table 1. transmitter operating modes data rate (mbits/sec) ratesel refsel dws word width (bits) reference clock frequency (mhz) 1062.5 1062.5 531.25 531.25 265.625 0 0 1 1 open 10 20 10 20 10 1 0 1 0 1 tclk/tclkn frequency (mhz) 53.125 53.125 53.125 26.5625 26.5625 106.25 53.125 53.125 26.5625 26.5625 1 0 1 0 1 parallel/serial conversion the parallel-to-serial converter takes in 10-bit or 20- bit wide data from the input latch and converts it to a serial data stream. parallel data is latched into the transmitter on the positive going edge of refclk. the data is then clocked synchronous to the clock synthesis unit serial clock into the serial output shift register. the shift register is clocked by the internally generated bit clock which is 10 times the refclk input frequency. the state of the serial outputs is controlled by the output enable pins, oe0 and oe1. d10 is transmitted first in 10-bit mode. d0 is trans- mitted first in 20-bit mode. table 2 shows the mapping of the parallel data to the 8b/10b codes. 10-bit/20-bit mode the S2042 operates with either 10-bit or 20-bit par- allel data inputs. word width is selectable via the dws pin. in 10-bit mode, d10Cd19 are used and d0Cd9 are ignored. first data byte second data byte 19 18 17 16 15 14 13 12 11 10 j h g f i e d c b a 9 8 7 6 5 4 3 2 1 0 tx[00:19] or rx[00:19] 8b/10b alphabetic representation j h g f i e d c b a first bit transmitted in 20-bit mode first bit transmitted in 10-bit mode table 2. data mapping to 8b/10b alphabetic representation figure 4. s2043 functional block diagram pll clock recovery 2:1 d 20 d bitclk q sync detect logic control logic rx refclk refsel ratesel lock_ref ry rlx rly lpen dws syncen lockdetn d(0..19) rclk sync rclkn shift register
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 4 high performance serial interface circuits S2042/s2043 s2043 receiver functional description the s2043 receiver is designed to implement the ansi x3t11 fibre channel specification receiver functions. a block diagram showing the basic chip function is provided in figure 4. whenever a signal is present, the s2043 attempts to achieve synchronization on both bit and transmis- sion-word boundaries of the received encoded bit stream. received data from the incoming bit stream is provided on the devices parallel data outputs. the s2043 accepts serial encoded data from a fiber optic or coaxial cable interface. the serial input stream is the result of the serialization of 8b/10b encoded data by an fc compatible transmitter. clock recov- ery is performed on-chip, with the output data presented to the fibre channel transmission layer as 10- or 20-bit parallel data. the chip is program- mable to operate at the fibre channel specified operating frequencies of 1062, 531 and 266 mbit/s. serial/parallel conversion serial data is received on the rx, ry pins. the pll clock recovery circuit will lock to the data stream if the clock to be recovered is within 100 ppm of the inter- nally generated bit rate clock. the recovered clock is used to retime the input data stream. the data is then clocked into the serial to parallel output regis- ters on the low going edge of rclk. in 1062 mbit/ sec, 10-bit mode, data is clocked out on the falling edge of rclk and rclkn.the parallel data out can be either 10 or 20 bits wide determined by the state of the dws pin. the word clock (rclk) is synchro- nized to the incoming data stream word boundary by the detection of the fiber channel k28.5 synchroniza- tion pattern (0011111010, positive running disparity). 10-bit/20-bit mode the s2043 will operate with either 10-bit or 20-bit parallel data outputs. this option is selectable via the dws pin. see table 4. in 10-bit mode, d10-d19 are used and d0-d9 are driven to the logic high state. reference clock input the reference clock input must be supplied with a single- ended ac coupled crystal clock source at 100 ppm tolerance. see table 4 for reference clock frequencies. framing the s2043 provides sync character recognition and data word alignment of the ttl level compatible output data bus. in systems where the sync detect function is undesired, a low on the syncen input disables the sync function and the data will be un-framed. first data byte second data byte 19 18 17 16 15 14 13 12 11 10 j h g f i e d c b a 9 8 7 6 5 4 3 2 1 0 tx[00:19] or rx[00:19] 8b/10b alphabetic representation j h g f i e d c b a first bit received in 20-bit mode first bit received in 10-bit mode table 3. data mapping to 8b/10b alphabetic representation refclk (input) rclk (output) sync (output) parallel data bus (input) k28.5, byte 1 of data byte 2, 3 of data byte 4, 5 of data byte 6, 7 of data byte 8, 9 of data byte 10, 11 of data byte 12, 13 of data byte 14,15 of data k28.5 byte 16 of data d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 parallel data bus (output) serial data s 2 0 4 2 s 2 0 4 3 k28.5 k28.5, byte 1 of data byte 2, 3 of data byte 4, 5 of data byte 6, 7 of data byte 8, 9 of data byte 10, 11 of data byte 12, 13 of data byte 14,15 of data k28.5 d16 figure 5. functional waveform
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 5 high performance serial interface circuits S2042/s2043 when framing is disabled by low syncen, the s2043 simply achieves bit synchronization within 250 bit times and begins to deliver parallel output data words whenever it has received full transmission words. no attempt is made to synchronize on any particular incoming character. the syncen input should be static during operation (i.e. connected to vcc or gnd). the s2043 will not main- tain the existing byte synchronization when syncen transitions from the active to inactive state. the sync output signal will go high whenever a k28.5 character (positive disparity) is present on the parallel data outputs. the sync output signal will be low at all other times. this is true whether the s2043 is operating in 10-bit mode or in 20-bit mode. in 20- bit mode, the k28.5 byte will always be placed in the msb (d0-d9). in 10-bit mode, the k28.5 will be clocked with the rclkn output. lock detect the s2043 lock detect function indicates the state of the phase-locked loop (pll) clock recovery unit. the pll will indicate lock within 250 bit times after the start of receiving serial data inputs. if the serial data inputs have an instantaneous phase jump (from a serial switch, for example) the pll will not indicate an out-of-lock state, but will recover the correct phase alignment within 250 bit times. if a run length of 64 bits is exceeded, or if the transition density is less than 12%, the loop will be declared out of lock and will attempt to re-acquire bit synchronization. when lock is lost, the pll will shift from the serial input data to the reference clock, so that correct frequency downstream clocking will be maintained. in any transfer of pll control from the serial data to the reference clock, the rclk/rclkn output remains phase continuous and glitch free, assuring the integ- rity of downstream clocking. table 4. receiver operating modes data rate (mbits/sec) ratesel refsel dws word width (bits) reference clock frequency (mhz) 1062.5 1062.5 531.25 531.25 265.625 0 0 1 1 open 10 20 10 20 10 1 0 1 0 1 rclk/rclkn frequency (mhz) 53.125 53.125 53.125 26.5625 26.5625 106.25 53.125 53.125 26.5625 26.5625 1 0 1 0 1 start-up procedure the clock recovery pll requires an initilization proce- dure to correctly achieve lock on the serial data inputs. at power-up or loss of lock, the pll must first acquire frequency lock to the local reference clock. this can be accomplished in three ways: 1) the Clock_ref pin can be connected to a 10 ms reset signal to initialize the pll. 2) by guaranteeing that no data is seen at the serial data inputs for a minimum of 10 ms upon power- up. 3) the s2043 can be put into the loopback mode and the loopback outputs of the S2042 must be quies- cent for a minimum of 10 ms after power-up. other operating modes loopback local loopback requires a S2042 and a s2043 as shown in the figure 6. when enabled, serial data from the S2042 transmitter is sent to the s2043 receiver, where the clock is extracted and the data is deserialized. the parallel data is then sent to the subsystem for verifica- tion. this loopback mode provides the capability to perform offline testing of the interface to guarantee the integrity of the serial channel before enabling the trans- mission medium. it also allows system diagnostics. operating frequency range the S2042 and s2043 are optimized for operation at the fibre channel rates of 266, 531 and 1062 mbit/s. operation at other than fibre channel rates is pos- sible if the rate falls within 10% of the nominal rate. refclk must be selected to be within 100 ppm of the desired byte or word clock rate. test modes the test pin on the S2042 and the syncen pin on the s2043 provide a pll bypass mode that can be used for operating the digital area of the chip. in this mode, clock signals are input through the reference clock pins. this can be used for testing the device during the manufacturing process or during an off- line self-test. sync detection is always enabled in test mode. figure 6. loopback interface diagram data in S2042 fibre channel transmitter s2043 fibre channel receiver clk data out local loopback s2043 fibre channel receiver S2042 fibre channel transmitter local loopback oe0, oe1 clk data out data in oe0, oe1
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 6 high performance serial interface circuits S2042/s2043 S2042 pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 9 1 d 8 1 d 7 1 d 6 1 d 5 1 d 4 1 d 3 1 d 2 1 d 1 1 d 0 1 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d l t ti 0 5 9 4 8 4 7 4 4 4 3 4 2 4 1 4 8 3 7 3 6 3 5 3 1 3 0 3 9 2 8 2 5 2 4 2 3 2 2 2 e g d e g n i s i r e h t n o n i d e k c o l c s i a t a d . a t a d t u p n i l e l l a r a p s t p e c c a t i b - 0 1 n i . t s r i f d e t t i m s n a r t s i 0 d , e d o m t i b - 0 2 n i . k l c f e r f o s i 0 1 d d n a , d e r o n g i e r a 9 d - 0 d , d e s u e r a 9 1 - 0 1 d , e d o m . t s r i f d e t t i m s n a r t t s e tc i t a t s - i t l u m l e v e l l t t i0 2, d e t c e n n o c t o n n e h w . g n i t s e t y r o t c a f r o f d e s u t u p n i l e v e l i t l u m y r o t c a f e t a t i l i c a f o t k c o l c t i b l a n r e t n i e h t s e c a l p e r k l c f e r . d n u o r g o t d e r i w s i t u p n i s i h t , e s u l a m r o n n i . g n i t s e t s w d l t t i9 1n e h w . h t d i w s u b a t a d l e l l a r a p e h t s t c e l e s n i p s i h t n o l e v e l e h t e r a ) 9 1 - 0 ( d d n a , d e t c e l e s s i h t d i w s u b l e l l a r a p t i b - 0 2 a , w o l - 0 1 ( d , d e t c e l e s s i s u b a t a d l e l l a r a p t i b - 0 1 a , h g i h n e h w . e v i t c a g n i s i r a ) . 1 e l b a t e e s ( . d e s u t o n e r a ) 9 - 0 ( d d n a e v i t c a e r a ) 9 1 . ) t s e t r o f d e s u ( t r a p e h t t e s e r l l i w e g d e k l c f e rl c e pi6 1e c n e r e f e r d e l l o r t n o c - l a t s y r c a ) . d e l p u o c y l e v i t i c a p a c y l l a n r e t x e ( s i k l c f e r f o y c n e u q e r f e h t . r e i l p i t l u m k c o l c l l p e h t r o f k c o l c ) . 1 e l b a t e e s ( . n i p l e s f e r e h t y b t e s k l c t n k l c t . f f i d l t t o2 1 1 1 e e s . t n e m e l p m o c d n a e u r t k c o l c e t a r d r o w l t t l a i t n e r e f f i d . y c n e u q e r f r o f 1 e l b a t y t x t . f f i d l c e p o9 8 e v i r d d n a a t a d l a i r e s e h t t i m s n a r t t a h t s t u p t u o l c e p l a i t n e r e f f i d 5 7w 0 5 r ow e h t s i x t . 0 e o y b d e l b a n e . v 2 - c c v o t n o i t a n i m r e t . t u p t u o e v i t a g e n e h t s i y t d n a , t u p t u o e v i t i s o p x l t y l t . f f i d l c e p o5 4 x t o t t n e l a v i u q e y l l a n o i t c n u f e r a t a h t s t u p t u o l c e p l a i t n e r e f f i d . g n i t s e t k c a b p o o l r o f d e s u e b o t d e d n e t n i e r a y e h t . y t d n a . 1 e o y b d e l b a n e
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 7 high performance serial interface circuits S2042/s2043 S2042 pin assignment and descriptions (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 0 e oc i t a t s l t t i2 l l i w y t / x t . s t u p t u o y t / x t r o f l o r t n o c e l b a n e - t u p t u o w o l e v i t c a . d e l b a s i d n e h w e t a t s w o l c i g o l e h t o t o g 1 e o l t t i1 y l t / x l t . s t u p t u o y l t / x l t r o f l o r t n o c e l b a n e - t u p t u o w o l e v i t c a . d e l b a s i d n e h w e t a t s w o l c i g o l e h t o t o g l l i w l e s f e rc i t a t s - i t l u m l t t i8 1. y c n e u q e r f k c o l c e c n e r e f e r e h t t c e l e s o t d e s u t u p n i l e v e l i t l u m ) . 1 e l b a t e e s ( l e s e t a r l t t i5 1e h t f o d e e p s g n i t a r e p o e h t t c e l e s o t d e s u t u p n i l e v e l i t l u m ) . 1 e l b a t e e s ( . r e t t i m s n a r t c c v l c ev 3 . 3 +C , 9 3 , 1 2 5 4 v 3 . 3 + e r o c d n g l t td n gC 4 1d n u o r g l t t c c v l t t/ v 3 . 3 + v 5 + C7 1) l t t f i v 5 + ( y l p p u s r e w o p l t t c c v o i l c ev 3 . 3 +C 0 1 , 3y l p p u s r e w o p o / i l c e p e e v o i l c ed n gC 7 , 6y l p p u s r e w o p o / i l c e p c c v av 3 . 3 +C 2 3 , 7 2y l p p u s r e w o p g o l a n a e e v ad n gC 3 3 , 6 2d n u o r g g o l a n a e e v l c ed n gC , 4 3 , 3 1 , 6 4 , 0 4 2 5 , 1 5 d n u o r g e r o c
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 8 high performance serial interface circuits S2042/s2043 s2043 pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 9 1 d 8 1 d 7 1 d 6 1 d 5 1 d 4 1 d 3 1 d 2 1 d 1 1 d 0 1 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d l t to 5 4 3 4 2 4 0 4 8 3 7 3 5 3 4 3 2 3 1 3 9 2 8 2 5 2 4 2 2 2 1 2 8 1 7 1 5 1 4 1 s i s u b a t a d l e l l a r a p e h t f o h t d i w e h t . s t u p t u o a t a d l e l l a r a p s i s u b s i h t n o a t a d l e l l a r a p . n i p s w d e h t f o e t a t s e h t y b d e t c e l e s n o d n a e d o m t i b - 0 2 n i k l c r f o e g d e g n i l l a f e h t n o t u o d e k c o l c , c e s / t i b m 5 . 2 6 0 1 n i n k l c r d n a k l c r f o s e g d e g n i l l a f e h t h t o b t i b - 0 1 n i . d e v i e c e r t i b t s r i f e h t s i 0 d , e d o m t i b - 0 2 n i . e d o m t i b - 0 1 h g i h e h t o t n e v i r d e r a 9 d - 0 d d n a d e s u e r a 9 1 d - 0 1 d , e d o m . d e v i e c e r t i b t s r i f e h t s i 0 1 d , e d o m t i b - 0 1 n i . e t a t s n t e d k c o ll t to 2 5e h t o t d e k c o l s i l l p e h t t a h t s e t a c i d n i n t e d k c o l , w o l n e h w g a l f m e t s y s a s e d i v o r p t i , h g i h n e h w . m a e r t s a t a d g n i m o c n i . k c o l c e c n e r e f e r l a c o l e h t o t d e k c o l s i l l p e h t t a h t g n i t a c i d n i n e p ll t ti8 t u p n i l a i r e s l a i t n e r e f f i d k c a b p o o l e h t s t c e l e s n e p l , h g i h n e h w . ) n o i t a r e p o l a m r o n ( y r d n a x r s t c e l e s n e p l , w o l n e h w . s n i p s w dc i t a t s l t t i4 n e h w . h t d i w s u b a t a d l e l l a r a p e h t s t c e l e s n i p s i h t n o l e v e l e h t e r a ) 9 1 - 0 ( d d n a , d e t c e l e s s i h t d i w s u b l e l l a r a p t i b - 0 2 a , w o l - 0 1 ( d , d e t c e l e s s i s u b a t a d l e l l a r a p t i b - 0 1 a , h g i h n e h w . e v i t c a g n i s i r a ) . 4 e l b a t e e s ( . h g i h o g l l i w ) 9 - 0 ( d d n a e v i t c a e r a ) 9 1 . ) t s e t r o f d e s u ( s r e t n u o c l a n r e t n i e h t t e s e r l l i w e g d e k l c r n k l c r . f f i d l t t o9 4 8 4 n k l c r / k l c r f o e g d e g n i l l a f e h t n o t u o d e k c o l c s i a t a d l e l l a r a p s i d r o w c n y s a r e t f a . ) 8 1 - 5 1 s e r u g i f n i s m a r g a i d g n i m i t e e s ( s i n k l c r d n a k l c r t n e r r u c e h t f o d o i r e p e h t , d e t c e t e d r o f 4 e l b a t e e s ( . y r a d n u o b d r o w e h t h t i w n g i l a o t d e h c t e r t s ) . y c n e u q e r f k l c f e rg o l a n ai2 - l a t s y r c g n i n n u r - e e r f a ) . d e l p u o c y l e v i t i c a p a c y l l a n r e t x e ( e h t . r e i l p i t l u m k c o l c l l p e h t r o f k c o l c e c n e r e f e r d e l l o r t n o c ) . 4 e l b a t e e s ( . n i p l e s f e r e h t y b t e s s i k l c f e r f o y c n e u q e r f c n y sl t to 1 5r o f h g i h s e o g t u p t u o s i h t , l o b m y s c n y s d i l a v a f o n o i t c e t e d n o p u e b l l a h s l o b m y s c n y s e h t , e v i t c a s i c n y s n e h w . d o i r e p k l c r e n o d n a e d o m t i b - 0 2 n i 9 d - 0 d s t i b s u b a t a d l e l l a r a p e h t n o t n e s e r p . e d o m t i b - 0 1 n i 9 1 d - 0 1 d x l r y l r . f f i d l c e p i1 1 2 1 a t a d k c a b p o o l l a i r e s e h t ) . d e l p u o c y l e v i t i c a p a c y l l a n r e t x e ( . t u p n i e v i t a g e n e h t s i y l r d n a , t u p n i e v i t i s o p e h t s i x l r . s t u p n i x r y r . f f i d l c e p i9 0 1 a t a d l a i r e s d e v i e c e r e h t ) . d e l p u o c y l e v i t i c a p a c y l l a n r e t x e ( . t u p n i e v i t a g e n e h t s i y r d n a , t u p n i e v i t i s o p e h t s i x r . s t u p n i
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 9 high performance serial interface circuits S2042/s2043 s2043 pin assignment and descriptions (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d n e c n y sc i t a t s - i t l u m l e v e l l t t i3 f o n o i t c e t e d . n o i t c e t e d c n y s s e l b a n e , h g i h n e h w ) . l e v e l i t l u m ( ) y t i r a p s i d g n i n n u r e v i t i s o p , 0 1 0 1 1 1 1 1 0 0 : 5 . 8 2 k ( n r e t t a p c n y s e h t n e p o n e h w . w o l l o f o t a t a d e h t r o f y r a d n u o b d r o w e h t e l b a n e l l i w e t a t i l i c a f o t k c o l c t i b l a n r e t n i s e c a l p e r k l c f e r , ) d e t c e n n o c t o n ( s i n o i t c e t e d c n y s , n o i t a r e p o f o e d o m s i h t n i . g n i t s e t y r o t c a f . a t a d d e m a r f n u s a d e t a e r t s i a t a d , w o l n e h w . d e l b a n e s y a w l a l e s f e rc i t a t s - i t l u m l e v e l l t t i0 3. y c n e u q e r f k c o l c e c n e r e f e r e h t t c e l e s o t d e s u t u p n i ) . l e v e l i t l u m ( ) . 4 e l b a t e e s ( l e s e t a rc i t a t s - i t l u m l e v e l l t t i0 2e h t f o d e e p s g n i t a r e p o e h t t c e l e s o t d e s u t u p n i ) . l e v e l i t l u m ( ) . 4 e l b a t e e s ( . r e v i e c e r f e r _ k c o ll t ti 0 5d n a t u p n i k l c f e r e h t o t k c o l o t l l p e h t s e c r o f , w o l n e h w . s t u p n i a t a d l a i r e s e h t e r o n g i c c v l c ev 3 . 3 +C , 7 2 , 3 1 9 3 y l p p u s r e w o p e r o c d n g l t td n gC , 3 3 , 6 1 6 4 , 1 4 d n u o r g l t t c c v l t t/ v 3 . 3 + v 5 + C, 3 2 , 9 1 4 4 , 6 3 ) l t t f i v 5 + ( y l p p u s r e w o p l t t c c v av 3 . 3 +C7 y l p p u s r e w o p g o l a n a e e v ad n gC 6 , 5d n u o r g g o l a n a e e v l c ed n gC 7 4 , 6 2 , 1d n u o r g e r o c
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 10 high performance serial interface circuits S2042/s2043 1 2 3 4 5 6 7 8 9 10 11 16 17 18 19 20 21 22 23 24 25 26 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 s2043 28 27 eclvcc d15 d14 ttlvcc d13 d12 ttlgnd d11 d10 refsel d9 d8 eclvcc 14 15 ttlgnd d2 d3 ttlvcc ratesel d4 d5 ttlvcc d6 d7 eclvee d0 d1 52 51 lck_ref rclk rclkn eclvee ttlgnd d19 ttlvcc d18 d17 ttlgnd d16 lockdetn sync 12 13 eclvee refclk syncen dws avee avee avcc lpen rx ry rlx rly eclvcc 1 2 3 4 5 6 7 8 9 10 11 16 17 18 19 20 21 22 23 24 25 26 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 S2042 28 27 eclvcc d11 d10 d9 d8 eclvee avee avcc d7 d6 d5 d4 avcc 14 15 refclk ttlvcc refsel dws test eclvcc d0 d1 d2 d3 avee ttlgnd ratesel 52 51 d19 d18 d17 d16 eclvee eclvcc d15 d14 d13 d12 eclvee eclvee eclvee 12 13 oe1 oe0 ecliovcc tly tlx ecliovee ecliovee tx ty ecliovcc tclkn tclk eclvee top view top view figure 7. 52 pqfp pinouts ttlvcc= +5v or +3.3v avcc= +3.3v eclvcc= +3.3v ecliovcc = +3.3v ecliovee = 0v ttlgnd= 0v eclvee= 0v avee= 0v
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 11 high performance serial interface circuits S2042/s2043 figure 8. 52 pqfp package
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 12 high performance serial interface circuits S2042/s2043 parameter min typ max unit case temperature under bias -55 125 c junction temperature under bias -55 150 c storage temperature -65 150 c voltage on vcc with repect to gnd -0.5 +7.0 v voltage on any ttl input pin -0.5 +5.5v v voltage on any pecl input pin 0 vcc v ttl output sink current 8 ma ttl output source current 8 ma high speed pecl output source current 50 ma static discharge voltage 500 v absolute maximum ratings recommended operating conditions parameter min typ max unit ambient temperature under bias 0 70 c junction temperature under bias 130 c voltage on ttlvcc with respect to gnd 5v operation 3.3v operation 4.75 3.13 5.0 3.3 5.25 3.47 v v voltage on any ttl input pin 0 ttlvcc v voltage on eclvcc with respect to gnd 3.13 3.3 3.47 v voltage on any pecl input pin eclvcc -2.0v eclvcc v reference clock requirements parameters description min max units conditions ft ft td 1 -2 t rcr , t rcf frequency tolerance S2042 frequency tolerance s2043 symmetry refclk rise and fall time random jitter -100 -100 40 +100 +100 60 2 ppm ppm % ns ps duty cycle at 50% pt. 20 ?80% peak-to-peak
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 13 high performance serial interface circuits S2042/s2043 parameters description min typ units conditions v oh output high voltage (ttl) ?3.3v power supply ?3.3v power supply ?5v power supply 2.1 2.2 2.7 2.0 0 -500 max v v v v cc = min, i oh = -2.4ma v cc = min, i oh = -.1ma v cc = min, i oh = -1ma i cc supply current 123 160 ma outputs open, v cc = v cc max p d power dissipation .406 .554 w outputs open, v cc = v cc max v ol output low voltage (ttl) ?3.3v power supply ?5v power supply .5 .5 v v v cc = min, i ol = 2.4ma v cc = min, i ol = 4ma v ih v il i ih i il input high voltage (ttl) input low voltage (ttl) input high current (ttl) input low current (ttl) 5.5 0.8 50 -50 v v a a i h 1ma at v ih = 5.5v v in = 2.4v v in = 0.5v 440 600 d v inclk d v out single-ended refclk input swing serial output voltage swing 1300 1600 mv mv ac coupled 50 w to v cc -2.0v S2042 dc characteristics parameters description min typ units conditions v oh output high voltage (ttl) ?3.3v power supply ?3.3v power supply ?5v power supply 2.1 2.2 2.7 2.0 0 -500 max v v v v cc = min, i oh = -2.4ma v cc = min, i oh = -.1ma v cc = min, i oh = -1ma i cc supply current ?10-bit mode ?20-bit mode 187 194 256 267 ma ma outputs open, v cc = v cc max outputs open, v cc = v cc max p d power dissipation ?3.3v supply, 10-bit mode ?3.3v supply, 20-bit mode ?5v supply, 10-bit mode ?5v supply, 20-bit mode .617 .640 .728 .778 .887 .925 1.08 1.142 w w w w outputs open, v cc = v cc max outputs open, v cc = v cc max outputs open, v cc = v cc max outputs open, v cc = v cc max v ol output low voltage (ttl) ?3.3v power supply ?5v power supply .5 .5 v v v cc = min, i ol = 2.4ma v cc = min, i ol = 8ma v ih v il i ih i il input high voltage (ttl) input low voltage (ttl) input high current (ttl) input low current (ttl) 5.5 0.8 50 -50 v v a a i h 1ma at v ih = 5.5v v in = 2.4v v in = 0.5v 440 100 1300 d v inclk v diff single-ended refclk input swing 1300 mv mv ac coupled min. differential input voltage swing for differential pecl inputs s2043 dc characteristics
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 14 high performance serial interface circuits S2042/s2043 parameters transmitter output jitter allocation description min max units conditions t 1 t 2 t 3 t 4 t 5 t cr , t cf t sdr , t sdf t 6 t dc refclk to tclk data setup w.r.t. refclk data hold w.r.t. refclk data setup w.r.t. tclk data hold w.r.t. tclk tclk rise and fall time serial data rise and fall tclk to tclkn skew tclk, tclkn duty cycle 1.0 1.0 2.0 5 1 40 4.0 5.0 300 1 60 ns ns ns ns ns ns ps ns % 10% to 90%, tested on a sample basis. 20% to 80%, tested on a sample basis. tested on a sample basis. t j rms serial data output random jitter (rms) 20 ps rms, tested on a sample basis. measured with 1010 pattern. 100 ps peak-to-peak, tested on a sample basis. measured with idle pattern. serial data output deterministic jitter (p-p) t dj table 5. ac characteristics table 6. s2043 receiver timing parameters description min max units conditions t 3 t 4 t 5 t 6 t 7 t rcr , t rcf t dr , t df t sdr , t sdf t lock duty cycle input jitter tolerance rclk to rclkn skew data set-up time data hold time data set-up time data hold time rclk rise and fall time data output rise and fall time serial data input rise and fall data acquisition lock time @ <1.0625gb/s rclk/rclkn duty cycle input data eye opening allocation at receiver input for ber 1e?2 3.0 1.5 2.5 7.5 40% 30% 1 5.0 5.0 300 2.4 60% ns ns ns ns ns ns ns ps s bit time tested on a sample basis. 1062 mbit/sec, 10-bit mode. 1062 mbit/sec, 10-bit mode. 1062, 531 mbit/sec, 20-bit mode. 531, 266 mbit/sec, 20-bit mode. 1062, 531 mbit/sec, 20-bit mode. 531, 266 mbit/sec, 20-bit mode. 10% to 90%, tested on a sample basis. 10% to 90%, tested on a sample basis. 20% to 80%. 8b/10b idle pattern sample basis as specified in fibre channel fc?h standard eye diagram jitter mask. note: all ac measurements are made from the reference voltage level of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). all ttl ac measurements are assumed to have the output load of 10pf. note: all ac measurements are made from the reference voltage level of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). all ttl ac measurements are assumed to have the output load of 10pf.
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 15 high performance serial interface circuits S2042/s2043 figure 9. transmitter timing diagram (531, 266 mbits/sec, 10-bit mode) d10 12 14 16 18 d10 12 14 16 18 11 13 15 17 d19 11 13 15 17 d19 t 6 t 4 t 5 t 2 t 3 t 1 serial data out tclk tclkn refclk 10 bit data (d10-d19) figure 10. transmitter timing diagram (531, 266 mbits/sec, 20-bit mode) d0 24681012141618 13 579 11131517 d19 t 6 t 4 t 3 t 2 t 5 t 1 serial data out tclk tclkn refclk 20 bit data
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 16 high performance serial interface circuits S2042/s2043 figure 11. transmitter timing diagram (1062 mbits/sec, 10-bit mode) d10 12 14 16 18 d10 12 14 16 18 11 13 15 17 d19 11 13 15 17 d19 t 6 t 4 t 5 t 2 t 3 t 1 serial data out tclk (53.125 mhz) tclkn (53.125 mhz) refclk (106.25 mhz) 10 bit data figure 12. transmitter timing diagram (1062 mbits/sec, 20-bit mode) d0 24681012141618 13 579 11131517 d19 t 6 t 4 t 3 t 2 t 5 t 1 serial data out tclk (53.125 mhz) tclkn (53.125 mhz) refclk (53.125 mhz) 20 bit data
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 17 high performance serial interface circuits S2042/s2043 figure 13. receiver timing diagram (531, 266 mbits/sec, 10-bit mode) figure 14. receiver timing diagram (531 mbits/sec, 20-bit mode) d10 12 14 16 18 d10 12 14 16 18 t 3 t 4 t 5 t 5 2.0v 1.4v .8v 11 13 15 17 d19 11 13 15 17 d19 t 4 serial data in refclk rclkn rclk 10 bit data sync k28.5 data d0 2 4 6 8 1012141618 t 3 t 6 t 7 1357911131517 d19 serial data in refclk rclk rclkn 20 bit data and sync
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 18 high performance serial interface circuits S2042/s2043 figure 15. receiver timing diagram (1062 mbits/sec, 10-bit mode) figure 16. receiver timing diagram (1062 mbits/sec, 20-bit mode) d0 2 4 6 8 1012141618 t 3 t 6 t 7 1357911131517 d19 serial data in refclk (53.125 mhz) rclk (53.125 mhz) rclkn (53.125 mhz) 20 bit data and sync d10 12 14 16 18 d10 12 14 16 18 t 3 t 4 t 5 t 5 2.0v 1.4v .8v 11 13 15 17 d19 11 13 15 17 d19 t 4 serial data in refclk (106.25 mhz) rclkn (53.125 mhz) rclk (53.125 mhz) 10 bit data sync k28.5 data
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 19 high performance serial interface circuits S2042/s2043 t r t f 80% 50% 20% 80% 50% 20% figure 17. serial input rise and fall time acquisition time with the input eye diagram shown in figure 21, the s2043 will recover data with a 10 -9 ber within 50 bit times after an instantaneous phase shift of the in- coming data. figure 21. acquisition time eye diagram .10 0 -0.2 0.2 0.3 0.5 0.7 0.8 1.0 1.3 0 .30 .40 .60 .70 .90 1.0 normalized time normalized amplitude figure 18. serial output load v dd - 2.0v 50 w figure 19.ttl input and output rise and fall time t r t f 90% 50% 10% 90% 50% 10% figure 20. receiver input eye diagram jitter mask amplitude bit time 30 %
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 20 high performance serial interface circuits S2042/s2043 transmitter 2042 grade package speed grade s C commercial ordering information 10 C 1062, 531, 266 mbit/s package 2043 receiver grade speed grade s C commercial b C 52 pqfp 10 C 1062, 531, 266 mbit/s x xxxx x C xx grade part number package speed grade b C 52 pqfp example: S2042b-05 S2042 in a 52 pqfp package operating at 531 or 266 mbit/sec rates. amcc is a registered trademark of applied micro circuits corporation. copyright ? 1997 applied micro circuits corporation june 2, 1997 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6195 lusk blvd., san diego, ca 92121 phone: (619) 450-9333 fax: (619) 450-9885 http://www.amcc.com

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